Monolithic 3D In General

MonolithIC3DChapter 1-Is the cost Reduction Associated withScaling over?by Zvi Or-Bach, the President and CEo of MonolithIC 3D IncYes, unless we Augment Dimensional Scaling with monolithic 3D-1C Scalingconductor industrymanifestation of moore' s law in dimensional scve to see with every new product cycle betterproducts at a lower cost But now storm clouds are forming as was recentlyexpressed"Nvidia deeply unhappy with TSMC, claims 20nm essentially worthlessclearly dimensional scalo longer associatedwer average cost pchart below, published by lBs about a yeahows the diminishingbenefit of cost reduction from dimensional scaling In fact, the chart indicates that20nm node might be associated with higher cost than the previous nodeFor the first time since we have started following the scaling roadmap,Jones sees an increase in cost gate at the 22 nod(8

9)(127)(40065nm4540nm3228nm2220nmTechno logy Nodele following Nvidia chart provides the first order explanatiof dimensional scaling resulted from doubling the number of transistors per wafer ButCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012-All Rights Reserved, Patents Pending

MonolithIC3Dhe wafer cost of the new technology node increases by too much then it neutralizesThe Nvidia chart shows thest of reche past (80nm, 55nm, 40nm) the incremental wafer cost increases werrapid depreciation of those costs resulted in almost constalRecent nodes(28nm, 20nm, 14nm,), however, signal a new realityWafer price is hiking upnVIDIAWafer price increases fromN2N, and the increase isgetting worseThe wafer price increase washes away the scaling benefit-> littlesaving in Xtor costneed to lower Coo, simplifyield

etc to incentivize Fab customers to 20 and 14nmCollaborate to move to bigger(450mm) wafershe following busy slide of IBM summarizes it clearly: "Net: neither per waferper gate showing historical cost reduction trendsCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 13

MonolithIC3DIs there a problemincreased node to nodePricing: Xover on Transistor Cost(Thprecluded new Lithographicsolutions such as EUVcomplex patterning solutionsgate showing historical cost32 nmImmersion/2nm6::hp地mLitho node (nm)SA Silicon Summit 2012 (SS

lyer)e number one drivelthe increase of wafer cost is the increase in theequipment cost required for processing the next technology node The following chartpresents the increase in costs of capital, process R&D, and desigIncreased Cost of Capital, R&D, DesignCost Associated with Node Progression Has Been Rising SignificantlyFa: cestChpDesgn CetndwangFasieCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 14

MonolithIC3Dhe sharp increase of costs associated with scaling is a new phenomenonnode to the next, but they were abconstant or incrementally smalClearly, for many nodes we were able to use the same lithography tools But oncedimensional scaling reached the limit of light wavelength the lithography tcritical and dominant About for every node the lithography became a major challengehat required newer equipment and substantial process R&D

Moreover, in the recerthography nodes the transistor itself required significant innovation at every node(hik, Metal Gate, Strain, SiGe, Tri-gate,)and it is clear that future scaled nodesContinuous Innovation Enables continuation of moore ' s law00◆08200mm◆05◆018◆90nmNiSi Strain, Low-k◆65Technologysuin,sie◆◆28mmEnablersTri-gate(3D)198019851990995200020052010reSearch corporationALamAn important part of these costs is the escalating cost of the capital equipmentfor the next node fabrication lines the following figure present the cost dynamic for theCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 15

MonolithIC3D◆Ar= Immersion▲ArF-DryKrF-DUV◆G&|Line01■ Broadband0

01196019802002020Yearography tools grew from less than 10% of wafer fab equipment (WFE)spending to over 25% and accordingly lithography now represents about 50 of thwater cosAn interesting implication of growing domination of lithography in semiconductorprocessing is the fact that the ASML, which is the lead vendor of lithography tooecently passed Applied Materials(thether tools)market cap Followinghe chart of the stock price of ASML (in red)vs Applied Material (AMADct 2009 Apra Dct 2011Copyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 16

MonolithIC3Dhe clear conclusion of all of this is that future dimensional scaling is not about tochange thesestated in the IBMwafer nor per gate showing historical cost reduction trends " UnlessUnless we change the way we do scaling(remember Einstein's famous guote)ber of transistoring was one of the three trends Moore described that wouldenable the observed and predicted exponential increase of device integration It woeem that it is about time to look on another one of those-increasing the die size If wedo it by using the 3rd dimension monolithic 3D-IC- we can achieve both higherntegration and cost reductiont is not that we should stop scaling down, it just that if we augment it with scalingtroduce the required changes that can achieve the continuation of the costreduction trend Clearly almost all of the increases of wafer costs are related to the pacedimensional scaling

If those costs could be spread over four years instead of twen the increase in wafer cost would be only about half of what it is nowht not be so clear, however, why monolithic 3D should reduce wafer costShouldn ' t the cost of the double die size spread over two layers be at least double?Monolithic 3D IC would reduce wafer cost because of the following elementsReduced Die Size- It has been shown in many research studies that eackg into 3d has the potential to reduce the total required silicon area by 50% due toduced re-buffering and reduced sizing of the buffersfew addheterogeneous Integration Scaling up would enable heterogeneousegration This will open up the third trend of Moore- improved circuit design As eachtrata of 3D ic could be processed in a different flow, cost and power could be saved byusing a different process flow for logic, memory and w/OCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012-All Rights Reserved, Patents Pending 17

Monolithic 3D In General

MonolithIC3DContentsChapter 1-is the cost reduction associated with scaling orChapter 22012-The Pivotal Point for monolithic 3D ICit twice thChapter 6-Low Temperature CleavingChapter 10interconnect:‖TCChapter 11-Can Heatc Stacks?Chapter 12-3D NAND Opens the Door for MonolithIC 3DPart 2: 3D-CMOS: Monolithic 3D104Chapter 13- The Way and How of Fine-Grain 3D IntegrationPart 3: 3D-FPGA: Monolithic 3D Programmable LogicChapter 14-Three Dimensional FPGAsapterPart 4: 3D-Gate Array: Monolithic 3D Gate Arraybedded Memory and MonolithIC 3DPart 5: 3D-Repair: Yield recovery for high-density chipChapter 17-Can Yield Increase with 3D Stacking?28Chapter 18-Monolithic 3D IC Could Increase Circuit Integration by 1,000xChapter 19- Repair in 3D Stack: The Path to 100% Yield with No Chip Size LimitsPart 6: 3D- DRAM: M3D DRAMChapter 20-Introducing our Monolithic 3D DRAM technologyart 7: 3D- RRAM: Monolithic 3D RRAMChapter 21-Introducing our Monolithic 3D Resistive Memory ArchitecturCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 3

MonolithIC3DChapter 22-The flas

h Industry' s direction and monolithIc 3D Inc's SolutionPart 9: Int sim v25Chapter 23-IntSim v2

MonolithIC3DAbout the authors of the e-bookZvi Or-BachPresident and CEoZvi Or-Bach is the founder of monolithic 3DTM Inc a finalist of the Best of semiconest 2011 for its monolithic 3D-IC breakthrough Or-Bach was also a finalist of theimes 2011 and 2012 Innovator of the Year Award for his pioneering workmonolithic 3D-ICsion ledst Structured ASIC architecture, the first single viaprogrammable array, and the first laser-based system for one-day Gate Arraycustomization In 2005

Or-Bach won the eetimes innovator of the year award andwas selected bmes to be part of the "Disruptors"--"The people, Products andTechnologies That Are Changing the Way we live, Work and play"Prior to monolithIc 3D Or-Bach founded basic in 1999 and served as theix years eASIC was funded by leading investors vinod Khosla and KPcthree successive rounds Under Or-Bach's leadership, eASIC won the prestigiousmes2005 ACE Award for Ultimate Product of the year in the Logic andProgrammable Logic categoryOr-Bach founded Chip Expre989(recently acquired by Gigoptix)anderved as the company,'s President and CEo for almost 10 years, bringing the companyo 40M revend to an industry recognition for three consecutive years as a highech Fast 50 Company that served over 1000 ASIC designs, including many one-dayprototypes and one-week production deliverbefore his entrepreneurial ventures in ASIC technology, Or-Bach held engineeringexingtolIssachusetts)cum laude in Electrical Engineering from the Technion-Israel Institute of Technology,and M Sc(1979)with distinction in Computer Science, from the Weizmann InstituteCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 5

MonolithIC3Dsrael

He holds over 100 issued or pending patents, primarily in the field of 3Dtegrated circuits and semi-custom chip architectuthe chairman of the boardor zeemiconductors Biaxial and visuMenu Or -Bachassionate about theemiconductor industry, and has participated in initiatives to improve immigrationand education policies to benefit the sameCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012-All Rights Reserved, Patents Pending 6

MonolithIC3DBrian CronquistViceBrian Cronquist has over 31 years of semiconductor industry experience, most recentlys Sr Dology Development& Foundry at non-volatile FPGa provider Actel Hehas global experience on " both sides of the silicon wafer table: starting and buildingChartered Semiconductor(Singapore)technology and customers as a captive then pureh)FPGa technology at Actepartner and customer to over 7 foundries and IDMs He also led startup wafer fabSierra Semiconductor

now PMC-Sierra, and developed newprocess technology at AMI and Synertek/HoneyweCronquist has a diverse technical interest which includes developing ultra-thind pre-cleargy(first to develop andplasma etching of metals and oxides, database scaling techniques, process simulationintegration novel ion imitechniques, first CMOS MOSFETs built with laser(Cw)annealing, minimizing process induced damage PID)from plasma etching and ionmplantation, time-to-market new product and process introduction(NPI), and customerengineering program managementhile at Actel, he was also principal Investigator of over $24M of government fundedhardened(RH) versions offuse andlash based product families in commercial and rh foundries He has published over 85the fieldemiconductor microelectronic radiation effects andhardening, as well as new logic, antifuse flash processes, devices, and reliability MiCronquist graduated cum laude (Chemistry Medal) in Chemistry from Santa ClaraUniversity in 1979 Currently, he is a visiting researcher at the Rice University ChemistryDepartment and an Industry Affiliate Partner at the Stanford University NanofabricationCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012-All Rights Reserved, Patents Pending

MonolithIC3DZe'ev wumaChief software architectWurman has over 30 years of experience in developing algorithms, CAD softwarehardware and software architectures Before monolithIC 3Dhe led the softwaredevelopment groups in Dyna Chip, an FPGA startup later acquired by Xilinx, and eAsIcPrior to that wurmantect for hardwaraccelerator at Amdahl, the largest and fastest hardware accelerator at theanaged CAD software for Silvar-Lisco, and spentwith IBM Resealalfa, Israel, working on algoatabases, and cryptography Between 2007 and 2009 Wurman served as senior policydviser in the office of plannialuation, and Policy Development, in the U

sDepartment of educationWurman holds B Sc and MSc degrees in Electrical Engineering from Technion, Israeogysrael He has published technical papersprofessional and trade journals and holds seven patentsCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 8

MonolithIC3DCTO Devicedustries From 1989 through 2006 he was a seniorechnologist and business executive at Applied Materials(NASDAQ: AMAT), the globalleader in semiconductor equipment, where he served in a variety of executive roles Heof thO)fornt group and later ctoApplied global services grolso served as the Chief Marketing Officer(CMO)he CmP division and CTo for the Thin Films Group (TFG) Dr Beinglass was involvedn numerous successful acquisitions and was a member of Applied Materials Strategyand Marketing councilse co-inventor of thedeveloper of selective Epieposition

He also was instrumental in developing the industrys first single-chamberpolysilicon deposition system and an integrated, multi-chamber Policide systerBefore joining Applied Materials, Dr Beinglass workedC(NASDAQ INTC) and IMP(NASDAQ: IMPX) in various positionsuding processdevelopment manager and engineering managee working attel he was the inventor of the selective tungsten deposition process He was a coecipient of the beatrice Winner Awarditorial ExcellenceIntl Solid StateCircuits Conference in 1982 He serves as a board member at noise free wireless andSpectros and used to serve as a board member at silicon genesis between 1998 and200glasss ScIence fromearch at UCSF andholder of 30 Uspatents(288 citations)as well as several pending patenCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 9

MonolithIC3DDeepak Sekar, Ph DDr Deepak sekar received a b tech from the Indianute of Technology(Madras)2003 and a Phd from the georgia Institute of Technology in 2008 He worked atSanDisk Corporation between 2006 and 2010, and conducted resealearly-2010 as a pas chief Scientist of the company and left the company in March 2012past 8 yearskars research has focusedPhDh involved doie of the fintal workcrochcooled 3D stacked chips

He also developed a CAd tool called Intsim that simulates 2Dnd 3D stacked systems At san Disk, Dr Sekar worked in the area of 3d crosspointmemory and developed rewritable memory devices, selector diodes and arrayarchitecturesissued or pending patents, predominantly in the field of 3D integration Awards he haseceived include a Best Student Paper Award at the Intl Interconnect TechnologyConference(2008), a Best Paper Award at theechnical Review(2009), an Intel(2008),twoAwards from the Semiconductor Research Corporation(2006, 2009)and the Nationalalent Scholarship from the Government of India(1997-2003)Committee Co-Chair at the International interconnect technology conference and asan Advisory board member for 3d InCitesCopyright MonolithIC 3D Inc, the Next-Generation 3D-IC Company, 2012 -All Rights Reserved, Patents Pending 10

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